Embodiments relate to the field of processors. In particular, embodiments relate to the field of processors that utilize paging.
Many processors and systems support virtual memory and paging. Paging may allow software to restrict and control accesses by processes or tasks to sections of memory referred to as pages. Paging may be used to create a separate or independent virtual address space for each process or task. This may be used to prevent one process or task from modifying the memory of other processes or tasks.
Commonly, pages may be accessed through a paging structure hierarchy or set of paging structures, such as a page directory and page tables. A page directory may have a number of page directory entries. Each page directory entry may store an indication of (e.g., a pointer to) a page table. The page table may represent a data structure used to map virtual addresses to physical addresses. A process or task may access the page table with a virtual address and use the page table to determine a physical address of the data it seeks. Each page table may have a number of page table entries. Each page table entry may store an indication of (e.g., a pointer to) the physical address of a page.
Many processors have a control register that is used to store information to locate the independent virtual address spaces and/or the paging structures that are appropriate for each process or task. For example, a page directory base register (PDBR) may be used to store a page directory base and/or a physical address of a page directory entry. When processes or tasks are scheduled, when process or task switches occur, or the like, the processes or tasks may modify the PDBR to store that processes or tasks corresponding page directory base.
Commonly, the attempted modifications of the PDBR or other control register are monitored for security purposes. However, inefficient monitoring of the PDBR modifications may tend to cause significant performance degradations.